The present invention relates to a memory controller, memory arrangement and memory access method and is particularly applicable for use in environments requiring high integrity of data stored in an auxiliary memory.
There are different architectures of memory controllers to suit different environments. In the case of the average home PC or even a business server, a single memory array is typically used for random access memory and loss of data due to a system crash, power failure or the like is considered unfortunate but not a disaster. Memory controller architectures have therefore evolved with the aim to protect the content of memory as best as is possible during standard operation without impacting on cost and usability of the computer.
However, in many environments, the integrity of data is key. For some, this is a regulatory requirement, for others it is essential that an accurate record of the state of a system, past transactions and the like has been captured.
For example, in slot machines and similar gaming machines, critical data needs to be maintained continuously, even after power cycle events, as it forms a record of what has happened on a machine and is a crucial method of countering fraud, amongst other uses In large jackpot situations, it is not uncommon for the entire machine to be taken away after a win and disassembled to ensure no tampering or data integrity issues exist.
As discussed above, this critical data needs to be maintained continuously, even after power cycle events. As it is necessary to be able to guarantee that data is written correctly, it is usual for this data to be stored in memory that has a fast access time. Any delays could mean data is not actually stored in the case of a power failure event. Random Access Memory (RAM) technology provides the necessary speed but conventional RAM does not maintain its stored data after a power cycle event. Therefore, non-volatile RAM (NVRAM) is often used in this environment. A requirement for use of NVRAM in machines is often contained within the technical specifications for slot machines laid down by the various regulatory bodies. The licensing of slot machines for use in particular jurisdictions normally requires demonstration and testing of compliance with these specifications.
As described above, maintaining the integrity of data that is stored in NVRAM under all circumstances is a crucial requirement. NVRAM performance is typically selected or designed to enable any critical data to be written before a power failure causes the system to stop functioning. In addition, mechanisms to protect against data corruption whilst not significantly impacting on NVRAM performance are desirable.
In order to attempt to achieve the resilience and performance desired, multiple (generally three) identical copies of the data are maintained, often spread across more than one physical memory device. The different areas of NVRAM where these copies of the data are stored are commonly referred to as “banks”.
Traditionally, NVRAM has been implemented using low-power SRAM (Static Random Access Memory) due to its high speed and the ability to retain data when power is removed by the use of batteries or other backup power sources. However, NVRAM can be made up from memory devices that are inherently non-volatile without the need for backup power sources. Flash memory is generally not a good solution due to poor write performance and block-based architecture that requires whole areas to be erased before new data can be written, along with the limited write endurance of flash technology. More recently, non-volatile RAM technologies such as MRAM (Magneto-restrictive Random Access Memory) have started to be used as the technology becomes more mature and cost effective. MRAM has the speed and random access of SRAM along with essentially infinite endurance.
It will be appreciated that the requirement for NVRAM based data storage is a critical and specialised part of systems such as slot machines. However, NVRAM based data storage is used as an auxiliary memory for specific purposes and does not generally form part of a standard computer system. This generally means the NVRAM controller logic that interfaces the CPU of the slot machine to the NVRAM is specifically designed to match the needs of the slot machine industry.
The volume of data that needs to be saved and the frequency of updates usually results in a designer selecting NVRAM that has high performance. Indeed, poor NVRAM performance can impact the functionality of the game, as updates need to be made at critical phases of the game. If NVRAM operations do not complete in a timely manner, it can cause poor responsiveness in the game, as certain operations cannot continue until the NVRAM data is updated to maintain an accurate record.
In recent years, PC technology has tended to replace proprietary computer architectures in slot machines, due to the high performance, excellent graphics capabilities and relatively low cost. The NVRAM remained a specialist requirement and there was included via an interface to the CPU that has therefore evolved over the years to follow PC general system architecture.
NVRAM capabilities usually form part of the “logic box” of a slot machine, either integrated onto the CPU board or onto a card plugged into an expansion slot or bus of the CPU board. The interface between the NVRAM memory devices and the CPU is generally designed to be as high speed as possible. Ideally, the interface would be connected as directly as possible to the memory bus of the CPU to maximise performance. However, it is important to note that the NVRAM memory is a separate logical block inside the computer system to the “main memory” that the processor uses to execute programs and store general data etc. As the performance of main memory is so critical to the overall performance of a computer system, it is usual that the CPU connects to main memory over a dedicated bus, which generally precludes connection of other memory devices. Hence all other peripherals and special memory devices, such as NVRAM, usually connect to the computer logic via more general purpose interface buses.
Whatever the bus used to connect the NVRAM to the computer system, there is necessarily some logic required to interface the native signals of the memory chips that comprise the NVRAM to the bus of the CPU. This interface logic matches the differing physical signals and the timings between the raw memory chips and the interface bus. This logic enables the NVRAM to appear in the memory or I/O address space of the computer system. In the past, buses of the computer system were relatively simple and the required logic was also straightforward. The buses present on more modem computer systems, such as PCI, are more complex and require more sophisticated interfaces. This extra complexity means the necessary interface logic is often implemented using programmable logic devices such as FPGAs. The job of this logic is simply to allow the NVRAM memory to be accessed by the CPU and also to make sure the NVRAM is protected when system power is removed. The CPU is responsible for reading, writing and the manipulation of all NVRAM data, including any copies.
In recent years, a new form of bus has come to dominate the PC industry called “PCI Express”. It is founded on the older PCI bus but provides for significantly faster data transfers using fewer physical signals. This is achieved by changing from a parallel-type bus (as in PCI) to a bus that is based on high speed serial bit streams. As the data is transmitted in serial form it has to be formatted into packets so that it can be correctly decoded at the receiving end, much like in a local area network (LAN). This requires even more sophisticated interface circuitry to interface the memory chips that comprise the NVRAM. This complexity precludes the use of simple logic for interfacing.
Although buses like PCI Express offer many benefits and potentially higher performance, they do have certain characteristics that are non-ideal for implementing NVRAM solutions. The most important of these drawbacks is latency. Although the data transfer bandwidth of a bus such as PCI Express (PCie) is faster than older, parallel type buses they suffer one disadvantage. All transactions between a PCie host and target require the request and any data to be assembled into a packet. In applications where large volumes of data are being sent in blocks (such as network traffic) this overhead is not significant. However, where small quantities of data need to be read from random locations the overhead can significantly impact overall performance. This can be in terms of bandwidth, but often more importantly in an application such as NVRAM for gaming, it can severely impact latency.
As the complexity and performance of gaming systems increases, the need for a high performance NVRAM function becomes more critical. With the random access nature of transactions with NVRAM, packet based buses such as PCI Express can introduce additional, latency related performance limitations. Typically the major impact to performance is with read cycles. With write cycles, modem computer architecture often “posts” write cycles, so they appear to complete quickly to the software. In fact the computer hardware is simply processing and “despatching” the write data in the background. This is not possible for read cycles, as the software requires the read data to be available before it can continue. Hence the hardware must complete the entire read operation and the software must wait.
In other applications of computers, read performance is often improved by the use of caching techniques—a copy of the data is kept in fast memory local to the CPU, and any request for data from the device is satisfied by the local cached copy that is available much more quickly. However, caching of NVRAM data in gaming is often not acceptable, as there is the possibility that differences could occur between the cached copy and the actual data stored in the NVRAM itself. So, for NVRAM in gaming read cycles are often the critical performance constraint.
Current NVRAM interface technology typically acts simply to make all NVRAM bank data available to the host processor. The NVRAM controller connects to the host CPU bus and takes care of translation of signals, protocols and timing etc. The NVRAM memory banks typically appear in the host processors memory (or I/O) address range, hence allowing the entire contents of NVRAM to be directly manipulated by the game software.